Regviz

Espressif Systems /ESP32-S2 /SPI0 /DMA_INT_ENA

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as DMA_INT_ENA

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/Espressif Systems/ESP32-S2/SPI0/DMA_INT_ENA#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (INLINK_DSCR_EMPTY_INT_ENA)INLINK_DSCR_EMPTY_INT_ENA 0 (OUTLINK_DSCR_ERROR_INT_ENA)OUTLINK_DSCR_ERROR_INT_ENA 0 (INLINK_DSCR_ERROR_INT_ENA)INLINK_DSCR_ERROR_INT_ENA 0 (IN_DONE_INT_ENA)IN_DONE_INT_ENA 0 (IN_ERR_EOF_INT_ENA)IN_ERR_EOF_INT_ENA 0 (IN_SUC_EOF_INT_ENA)IN_SUC_EOF_INT_ENA 0 (OUT_DONE_INT_ENA)OUT_DONE_INT_ENA 0 (OUT_EOF_INT_ENA)OUT_EOF_INT_ENA 0 (OUT_TOTAL_EOF_INT_ENA)OUT_TOTAL_EOF_INT_ENA 0 (INFIFO_FULL_ERR_INT_ENA)INFIFO_FULL_ERR_INT_ENA 0 (OUTFIFO_EMPTY_ERR_INT_ENA)OUTFIFO_EMPTY_ERR_INT_ENA 0 (SLV_CMD6_INT_ENA)SLV_CMD6_INT_ENA 0 (SLV_CMD7_INT_ENA)SLV_CMD7_INT_ENA 0 (SLV_CMD8_INT_ENA)SLV_CMD8_INT_ENA 0 (SLV_CMD9_INT_ENA)SLV_CMD9_INT_ENA 0 (SLV_CMDA_INT_ENA)SLV_CMDA_INT_ENA

Description

SPI DMA interrupt enable register

Fields

INLINK_DSCR_EMPTY_INT_ENA

The enable bit for lack of enough inlink descriptors. Can be configured in CONF state.
OUTLINK_DSCR_ERROR_INT_ENA

The enable bit for outlink descriptor error. Can be configured in CONF state.
INLINK_DSCR_ERROR_INT_ENA

The enable bit for inlink descriptor error. Can be configured in CONF state.
IN_DONE_INT_ENA

The enable bit for completing usage of a inlink descriptor. Can be configured in CONF state.
IN_ERR_EOF_INT_ENA

The enable bit for receiving error. Can be configured in CONF state.
IN_SUC_EOF_INT_ENA

The enable bit for completing receiving all the packets from host. Can be configured in CONF state.
OUT_DONE_INT_ENA

The enable bit for completing usage of a outlink descriptor . Can be configured in CONF state.
OUT_EOF_INT_ENA

The enable bit for sending a packet to host done. Can be configured in CONF state.
OUT_TOTAL_EOF_INT_ENA

The enable bit for sending all the packets to host done. Can be configured in CONF state.
INFIFO_FULL_ERR_INT_ENA

The enable bit for infifo full error interrupt.
OUTFIFO_EMPTY_ERR_INT_ENA

The enable bit for outfifo empty error interrupt.
SLV_CMD6_INT_ENA

The enable bit for SPI slave CMD6 interrupt.
SLV_CMD7_INT_ENA

The enable bit for SPI slave CMD7 interrupt.
SLV_CMD8_INT_ENA

The enable bit for SPI slave CMD8 interrupt.
SLV_CMD9_INT_ENA

The enable bit for SPI slave CMD9 interrupt.
SLV_CMDA_INT_ENA

The enable bit for SPI slave CMDA interrupt.

Links

()

Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

 ()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data